1. Field of the Invention
The present invention relates to a semiconductor memory and particularly to a single port static random-access memory (hereinafter also referred to as “SRAM” in a single word).
2. Description of Related Art
As an example, FIG. 14 is a circuit diagram that shows the design of a memory cell in a conventional Static Random Access Memory (SRAM).
This SRAM memory cell M100 shown in FIG. 14 comprises a latch circuit that includes a p-type MOS transistor P101 and an n-type MOS transistor N101, which are connected with each other in series between a supply voltage VCC and a ground voltage VSS, and another p-type MOS transistor P102 and another n-type MOS transistor N102, which are connected with each other in series between a supply voltage VCC and a ground voltage VSS.
The gate terminals of MOS transistors P101 and N101 are both connected to the junction T102 of MOS transistor P102 and N102, and the gate terminals of MOS transistors P102 and N102 are both connected to the junction T101 of MOS transistors P101 and N101. In other words, because these transistors are cross-coupled in connection, p-type MOS transistors P101 and P102 act as load transistors (load), and n-type MOS transistors N101 and N102 act as drive transistors (driver).
In addition, the SRAM memory cell M100 comprises: an n-type MOS transistor N103, which is connected between one of complementary bit line pair BL and the junction T101; and an n-type MOS transistor N104, which is connected between the other one of the complementary bit line pair XBL and the junction T102. The gates of n-type MOS transistors N103 and N104 are both connected to a common word line WL. Therefore, the gate electrical potentials of n-type MOS transistors N103 and N104 are controlled by the word line WL.
In this arrangement, p-type MOS transistors P101 and P102 act as load, n-type MOS transistors N101 and N102 act as driver, and n-type MOS transistors N103 and N104 act as transfer. As a result, the SRAM memory cell has a CMOS structure.
Now, the operation of the SRAM memory cell M100 is explained.
At first, as an example of reading operation for the SRAM memory cell M100, readout is considered for a case where junction T101 has a low level of electrical potential while junction T102 has a high level in the SRAM memory cell M100.
While the word line WL is at a low level of electrical potential before a reading operation of the SRAM memory cell M100, the supply voltage VCC is applied to bit lines BL and XBL for a predetermined pre-charging time. By this pre-charging, electricity is charged in the lines BL and XBL, the charge being stored up-to the charging capacities CBL and CXBL of the electric wirings. Therefore, after the completion of the pre-charging, the bit lines BL and XBL are kept approximately at the supply voltage VCC.
After the completion of the pre-charging time, a reading operation is executed by turning the word line WL to a high level of electrical potential. As a result, a readout current IR flows through n-type MOS transistor N103 and n-type MOS transistor N101 from bit line BL to the ground voltage VSS, and the electrical potential of the bit line BL is returned to the low level.
When this readout current IR flows, the voltage at junction T101 rises from a low level in correspondence to the ratio of the activated resistances of n-type MOS transistor N101 and n-type MOS transistor N103. By this voltage increase, the inverter comprising p-type MOS transistor P102 and n-type MOS transistor N102 should not be inverted. In other words, the voltage of the junction T101 must be prevented from exceeding a threshold voltage Vth at which the inverter is inverted. Therefore, the conductance of n-type MOS transistor N101 must be set greater than that of n-type MOS transistor N103 (N101>N103).
As the electrical potential of bit line XBL is kept at a high level, the electrical potentials of bit lines BL and XBL are at a low level and at a high level, respectively. This condition is detected by a sense amplifier (not shown), which uses the voltage difference between the bit lines BL and XBL as input, and the stored content of the SRAM memory cell M100 is read out.
Next, an example of writing operation is explained by assuming that junction T101 is at a high level while junction T102 is at a low level in the SRAM memory cell M100 before this writing operation takes place and that this writing operation turns junction T101 to a low level and junction T102 to a high level.
At first, by write-in amplifiers (not shown), a low level electrical potential is applied to bit line BL while a high level electrical potential is applied to bit line XBL. In addition, a high level electrical potential is applied to the word line WL. As a result, n-type MOS transistors N103 and N104 become conductive in the SRAM memory cell M100, and a write-in current IW flows through p-type MOS transistor P101 and n-type MOS transistor N103 from the supply voltage VCC to bit line BL.
When this write-in current IW flows, the voltage at junction T101 drops from the high level in correspondence to the ratio of the activated resistances of p-type MOS transistor P101 and n-type MOS transistor N103. Here, the inverter comprising p-type MOS transistor P102 and n-type MOS transistor N102 should be inverted. In other words, the voltage at junction T101 should drop beyond the threshold voltage Vth, at which the inverter is inverted. Therefore, the conductance of p-type MOS transistor P101 must be set smaller than that of n-type MOS transistor N103 (N103>P101).
When the voltage at junction T101 becomes lower than the threshold voltage Vth, the voltage at junction T102 is turned from the low level to the high level. As a result, the output of the inverter comprising p-type MOS transistor P101 and n-type MOS transistor N101 is turned from the high level to the low level, and the writing operation for the SRAM memory cell M100 completes.
As technologies relating to SRAM, Japanese Unexamined Patent Publication Nos. 2005-25863 and 2003-132684 disclose multi-port SRAMs.